1. Field of the Invention
This invention relates to a MOS transistor and a differential amplifier circuit using the same, and more particularly to the construction of a MOS transistor for lowering the offset voltage of a differential amplifier circuit, and a differential amplifier circuit of low offset voltage using the same.
2. Description of the Related Art
FIGS. 1A and 1B show a typical pattern shape and cross section of a conventional MOS transistor. Referring to FIGS. 1A and 1B, numeral 10 denotes an element region designed for forming a MOS transistor, and numeral 12 denotes an actually formed physical element region (SDG). As can be clearly seen in FIG. 1A, the dimensions of the actually formed element region 12 are smaller than the design dimensions, because of the bird's beak of the field insulation layer 13 formed by the LOCOS method. Since the channel length L of the MOS transistor is defined by the width of the gate electrode layer 11, it is not affected by a reduction in the dimensions of the element region; however, the channel width W thereof is defined by the width of a diffusion layer 14 used as a source or drain region and is therefore reduced to W', as shown in FIGS. 1A and 1B, due to the dimensions of the element region being smaller than the design dimensions.
Not only does a reduction in the channel width occur in every MOS transistor formed on a semiconductor chip by means of the conventional method, but the degree of difference between the design channel width W and the actual channel width W' may vary from one MOS transistor to another, since the dimensions of the bird's beak formed in the field insulation layer 13 are not constant and vary from one portion to another of the chip on which the field insulation layer 13 is formed. Consequently, when a plurality of MOS transistors of the same construction as shown in FIGS. 1A and 1B are formed on the same chip, the current characteristics may well vary from transistor to transistor.
In the case of a differential amplifier circuit, it is generally preferable to set the current characteristics of the differential input stage transistors equal to each other in order to suppress the offset voltage to a minimum. However, when the differential amplifier circuit is formed by use of MOS transistors of the construction as described before, the differential input stage transistors are likely to be formed having different channel widths, which makes it difficult to reduce the offset voltage.
A ring-shaped MOS transistor as shown in FIGS. 2A and 2B has been developed as a type the channel width of which is not affected by a reduction in the dimensions of the element region. FIG. 2A shows the pattern shape of this MOS transistor and FIG. 2B shows a cross section thereof. In the above MOS transistor, a diffusion region 24 formed inside a ring-shaped gate electrode layer 21 serves as a drain region, and a diffusion region 25 formed outside layer 21 serves as a source region. Numeral 20 denotes an element region designed for forming a MOS transistor and numeral 22 denotes an actually formed physical element region. As can be clearly seen in FIG. 2A, the dimensions of the actually formed element region 22 are smaller than the design dimensions, because of the bird's beak of the field insulation layer 13.
However, in the above MOS transistor, the channel length L is defined by the width of the annular portion of the ring-shaped gate electrode layer 21 and the channel width W is determined by the circumference of a circle formed halfway between the inner circumference of the ring-shaped gate electrode layer 21 and the outer circumference thereof, and is not influenced by the dimensions of the element region. Consequently, the transistor characteristic is not affected by any reduction in the dimensions of the element region.
The gate electrode layer 21 of the above transistor is formed independently in the element region and does not extend to the outside thereof. For this reason, it is necessary for a contact to be formed which directly connects the gate electrode layer 21 and a wiring on layer 21, in which case the dimensions of the contact area are determined by the width of the annular portion of layer 21.
Therefore, in order to obtain a sufficiently large contact area, it becomes necessary to increase the width of the annular portion of the gate electrode layer 21. However, any increase in the width of the annular portion causes a corresponding increase in the dimensions of the element of the MOS transistor, thereby preventing any increase in the integration density.